1. Field of the Invention
The invention relates generally to semiconductor integrated device design and fabrication and more particularly, to techniques for reducing stress induced charge leakage in VLSI memory arrays such as dynamic random access memories (DRAM).
2. Description of the Related Art
This invention relates to manufacturing processes used to create multilayer semiconductor circuit devices on silicon substrates such as VLSI and ULSI. Generally, these processes include isolation processes, which isolate the active areas of the semiconductor from each other and device implantation processes which result in devices such as transistors and the like being implanted into the active areas. These processes are used to produce, among other things, items such as memory cells. In the past several years the trend has been to produce chips having a higher density of active devices. In particular, DRAM memories are but one example of devices made with these manufacturing processes that have necessitated smaller dimension devices.
As the dimensions of individual memory cells in a DRAM array continue to shrink, the need for efficient and reliable isolation processes to separate active device regions dramatically increases. In fact, known processing techniques have become increasingly ineffective for memory cells and other devices having sub-micron dimensions. Specifically, to extend the use of LOCOS (for LOCal Oxidation of Silicon) isolation technology into sub-half-micron size for 256M DRAM generation, radical modifications in conventional processing technologies are needed.
LOCOS processing is widely used for device isolation applications in the semiconductor industry. Initially, in a conventional LOCOS process, a thin layer of silicon dioxide (SiO.sub.2) is grown on a silicon substrate. This initial layer of silicon dioxide is known as pad oxide in the LOCOS process. The function of this layer is to reduce stress between the silicon substrate and the subsequently deposited layers. Next, a layer of nitride is deposited on the pad oxide layer and lithographically defined to retain the nitride in the active device regions. The nitride is etched from the area between the active device areas where a thick, isolating silicon dioxide layer (field oxide) is to be grown. After the nitride is defined on top of the future active device areas, an oxide layer is thermally grown in the exposed silicon regions and the nitride acts essentially as an oxidation barrier to prevent most oxide growth in the active regions. During the process of oxidation, however, some of the oxidants diffuse laterally at the edges of the nitride masking stack. This causes the oxide layer to grow under and lift the edges of the nitride masking stack. The region of slowly tapering oxide that encroaches under the nitride stack into the active device areas is generally known as the bird's beak region, due to its shape.
Unfortunately, there are several problems that arise from this oxide encroachment under the nitride stack into the active device areas. First, the bird's beak region limits the usable active device areas in the active device region of the substrate. Second, the stress originating from this encroachment and the masking stack thickness increase the overall stress level which leads to the generation of defects in the silicon substrate. These stress induced defects increase the junction leakage current and, as such, reduce the overall reliability of the device.
The problems of the standard LOCOS process have motivated the development of better isolation schemes. In general, an ideal isolation technique should meet the following requirements. First, the spacing between active areas, e.g., the isolation regions, should be minimal to maximize the active area regions of the wafer. Second, the bird's beak region should be as small as possible. Third, the leakage current between active devices must be negligible. Fourth, the process for forming the isolation should not adversely affect the process parameters required for active device fabrication. Finally, the isolation process should be easy to implement and control.
Among a few other isolation technologies, which have focussed their effort on reducing the length of the bird's beak region, the Poly Buffered LOCOS (PBL) isolation process has demonstrated itself as a less complicated improvement on the conventional LOCOS process. PBL uses a polysilicon (poly) layer between the pad oxide and the nitride prior to field oxide growth. The presence of the intermediate polysilicon layer allows the oxide to be thinned and the nitride thickened without generating undue stress in the active regions in order to reduce encroachment during the field oxidation step. In general, a thinner pad oxide layer allows less oxide encroachment under the nitride stack because the downward compressing force from the nitride stack is transmitted more effectively to the substrate through a thinner oxide layer. Consequently, an approximate 50% reduction in length of bird's beak region can be achieved. Following the growth of field oxide the nitride masking stack layers are sequentially stripped (etched away) from the active area locations.
Unfortunately, in standard poly buffered LOCOS processing, the stripping process causes pitting on the surface of the substrate. During the stripping step of the polysilicon layer, the etchants used for stripping polysilicon penetrate into the substrate through the underlying pad oxide layer and develop cavities, i.e., pits, on the surface of the substrate. This cavity formation makes the active areas less usable for further device applications. The pitting becomes more severe as the active area dimensions are reduced to the submicron size.
It is believed that this particular problem with PBL initially begins with the diffusion of oxidants and ammonia along the masking stack layers, which are nitride, polysilicon and pad oxide on top of a silicon substrate, during field oxidation. The oxidants and ammonia diffusing along the pad oxide and polysilicon layers react with the surface of substrate and the top and bottom surfaces of the polysilicon layer to form silicon dioxide and nitride spots thereon. The oxidation and nitridation which proceed along the polysilicon grain boundaries result in some grain boundaries that are more nitride-like in characteristics and others more oxide-like. Hence, when the nitride layer is etched off, nitridized polysilicon grains are completely removed, thereby leaving pits on the polysilicon layer.
Further, during the removal of silicon dioxide residues from the top of the polysilicon layer, oxide etchant penetrates the underlying pad oxide layer through the pitted regions and etches the underlying pad oxide region thereby partially exposing the substrate. Consequently, during the etching step of the polysilicon layer, the polysilicon etchants attack these exposed regions of the substrate. This "pitting" phenomenon is further discussed in "Twin-White-Ribbon Effect and Pit formation Mechanism in PBLOCOS", by Tin-hwang Lin, et al., J. Electr. Chem. Soc., Vol. 138, No. 7, July 1991, pp. 2145-2149.
Techniques to alleviate the problems associated with PBL increase the complexity of the prior art PBL process and thereby increase the costs associated with manufacturing devices using the PBL process. Thus, there is a need to develop new processing techniques to reduce the length of bird's beak region encroachment into the active areas and the related defects while minimizing damage to the upper surface of the active device regions of the wafer during processing.